A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.
|Title of host publication||IEEE Computer Society Press, Intl. Conf. on Systolic Arrays, eds. K Bromley, E S Swartzlander Jr and S Y Kung|
|Number of pages||11|
|Publication status||Published - 01 Jan 1988|