Bit-level systolic arrays for IIR filtering.

S.C. Knowles; R.F. Woods; J.G. McWhirter; J.V. McCanny

Bit-level systolic arrays for IIR filtering.

S.C. Knowles, R.F. Woods, J.G. McWhirter, J.V. McCanny

Research output: Chapter in Book/Report/Conference proceeding › Other chapter contribution

Abstract

A novel bit-level systolic array architecture for implementing IIR (infinite-impulse response) filter sections is presented. A first-order section achieves a latency of only two clock cycles by using a radix-2 redundant number representation, performing the recursive computation most significant digit first, and feeding back each digit of the result as soon as it is available. The design is extended to produce a building block from which second- and higher-order sections can be connected.

Original language	English
Title of host publication	IEEE Computer Society Press, Intl. Conf. on Systolic Arrays, eds. K Bromley, E S Swartzlander Jr and S Y Kung
Pages	653-663
Number of pages	11
Publication status	Published - 01 Jan 1988

Cite this

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Bit-level systolic arrays for IIR filtering.

Abstract

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