Abstract
This paper describes the design and the architecture of a bit-level systolic array processor. The bit-level systolic array described is directly applicable to a wide range of image processing operations where high performance and throughput are essential. The architecture is illustrated by describing the operation of the correlator and convolver chips which are being developed. The advantage of the system is also discussed.
| Original language | English |
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| Journal | IEE Colloquium (Digest) |
| Issue number | 1983 /100 |
| Publication status | Published - 01 Jan 1983 |