BIT-LEVEL SYSTOLIC ARRAYS FOR SIGNAL AND IMAGE PROCESSING.

J.G. McWhirter, J.V. McCanny

Research output: Contribution to journalArticlepeer-review

Abstract

This paper describes the design and the architecture of a bit-level systolic array processor. The bit-level systolic array described is directly applicable to a wide range of image processing operations where high performance and throughput are essential. The architecture is illustrated by describing the operation of the correlator and convolver chips which are being developed. The advantage of the system is also discussed.
Original languageEnglish
JournalIEE Colloquium (Digest)
Issue number1983 /100
Publication statusPublished - 01 Jan 1983

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

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