Characterization of HPC workloads on an ARMv8 based server under relaxed DRAM refresh and thermal stress

Improving energy efficiency of the memory subsystem becomes increasingly important for all digital systems due to the rapid growth of data. Many recent schemes have attempted to reduce the DRAM power by relaxing the refresh rate, which may negatively affect the DRAM reliability. To optimize the trade-offs between power and reliability, existing studies rely on experimental setups based on FPGAs and the use of few known data-patterns for exciting rare worst-case circuit reliability effects. However, by doing so, existing studies may be missing to capture the real DRAM behavior within a commodity server with a fully fledged OS.

In this paper, we develop an experimental framework based on a state-of-the-art 64-bit ARM based server with Linux OS, in which we enabled the characterization of 72 DRAM chips under relaxed refresh period and various temperatures controlled by a unique thermal testbed. We evaluate the DRAM reliability running single and multi-threaded HPC workloads on such a commodity server with a fully-fledged Linux OS and a typical multilevel memory hierarchy. In fact, our results show that the manifested Word-ErrorRate under relaxed refresh period varies among the workloads and can be different from the one estimated by the few known fixed data-patterns that were conventionally used in all existing studies. We also discover that the error rates incurred by the execution of the HPC workloads may vary within a program run. Finally, our study shows that the refresh period can be relaxed by 35× leading to 11.2 % power savings on average, while avoiding any system disruption, since the available error-correcting-codes were able to correct all incurred errors up to 60 ◦C.