The implementation of a multi-bit convolver chip based on a systolic array is described. The convolver is fabricated on a 7mm multiplied by 8mm CMOS chip and operates on 8-bit serial data and coefficient words. It has a length of 17 stages, and this is cascadable. The circuit can be clocked at more than 20 MHz giving a data throughput rate of greater than 1 Mword/s. Details of important implementation decisions and a summary of chip characteristics are given together with the advantages which the systolic approach has afforded to the design process.
|Title of host publication||" VLSI 83, Trondheim, Norway 1983, North Holland|
|Number of pages||9|
|Publication status||Published - 01 Jan 1983|