CMOS IMPLEMENTATION OF A SYSTOLIC MULTI-BIT CONVOLVER CHIP.

R.A. Evans, D. Wood, K. Wood, J.V. McCanny, J.G. McWhirter, A.P.H. McCabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

The implementation of a multi-bit convolver chip based on a systolic array is described. The convolver is fabricated on a 7mm multiplied by 8mm CMOS chip and operates on 8-bit serial data and coefficient words. It has a length of 17 stages, and this is cascadable. The circuit can be clocked at more than 20 MHz giving a data throughput rate of greater than 1 Mword/s. Details of important implementation decisions and a summary of chip characteristics are given together with the advantages which the systolic approach has afforded to the design process.
Original languageEnglish
Title of host publication" VLSI 83, Trondheim, Norway 1983, North Holland
Pages227-235
Number of pages9
Publication statusPublished - 01 Jan 1983

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    Evans, R. A., Wood, D., Wood, K., McCanny, J. V., McWhirter, J. G., & McCabe, A. P. H. (1983). CMOS IMPLEMENTATION OF A SYSTOLIC MULTI-BIT CONVOLVER CHIP. In " VLSI 83, Trondheim, Norway 1983, North Holland (pp. 227-235)