CNTFET‐based ternary address decoder design

Rawan Mohammed, Mohammed E. Fouda, Ihsen Alouani, Lobna A. Said, Ahmed G. Radwan

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

With the end of Moore's law, new paradigms are investigated for more scalable computing systems. One of the promising directions is to examine the data representation toward higher data density per hardware element. Multiple valued logic (MVL) emerged as a promising system due to its advantages over binary data representation. MVL offers higher information processing within the same number of digits when compared with binary systems. Accessing memory is considered one of the most power- and time-consuming instructions within a microprocessor. In the quest for building an entire ternary computer architecture, we propose investigating the potential opportunities of ternary address decoders. This paper presents three different designs for ternary address decoder based on CNTFET. The first design is based on a cascade of Ternary to Binary blocks (T2B) and a binary decoder. The second design is built using the hierarchical structure and enables signals. The third is designed utilising a pre-decoder and ternary logic gates. A comparison of the proposed designs and the binary address decoder in terms of power and delay under different supply voltage and temperature values is introduced. Simulation results show that the second design has the least power and delay of the proposed ternary designs.
Original languageUndefined/Unknown
Pages (from-to)3682-3691
Number of pages10
JournalInternational Journal of Circuit Theory and Applications
Volume50
Issue number10
Early online date07 Jun 2022
DOIs
Publication statusPublished - Oct 2022

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