Abstract
Lattice-based cryptography is a quantum-safe alternative
to existing classical asymmetric cryptography, such as
RSA and ECC, which may be vulnerable to future attacks in the
event of the creation of a viable quantum computer. The efficiency
of lattice-based cryptography has improved over recent years, but
there has been relatively little investigation into hardware designs
of digital signature schemes. In this paper, the first hardware
design of the provably secure Ring-LWE digital signature scheme,
Ring-TESLA, is presented, targeting a Xilinx Spartan-6 FPGA.
The results better compactness of all previous lattice-based digital
signature schemes in hardware, and can achieve between 104-785
signatures and 102-776 verifications per second.
| Original language | English |
|---|---|
| Number of pages | 4 |
| Publication status | Accepted - 17 Feb 2017 |
| Event | IEEE International Symposium of Circuits and Systems - Baltimore, United States Duration: 28 May 2017 → 31 May 2017 http://iscas2017.org/ |
Conference
| Conference | IEEE International Symposium of Circuits and Systems |
|---|---|
| Abbreviated title | ISCAS |
| Country | United States |
| City | Baltimore |
| Period | 28/05/2017 → 31/05/2017 |
| Internet address |
Keywords
- lattice-based cryptography, digital signatures, postquantum cryptography, hardware security, FPGA