Abstract
This paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical SOI MOSFETs. The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. The origin of higher parasitic capacitance in FinFETs, compared to planar MOSFETs is examined. RF figures of merit for planar and vertical MOS devices are compared, based on layout-area calculations.
| Original language | English |
|---|---|
| Article number | 005 |
| Pages (from-to) | 481-491 |
| Number of pages | 11 |
| Journal | Semiconductor Science and Technology |
| Volume | 22(5) |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 01 Mar 2007 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- General Materials Science
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
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