Abstract
A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Attention is focused on a circuit which is used to multiply streams of parallel unsigned data. Then an algorithm is given which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features whch make it attractive to LSI and VLSI. These include regularity and modularity.
Original language | English |
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Pages (from-to) | 40-46 |
Number of pages | 7 |
Journal | IEE proceedings. Part G. Electronic circuits and systems |
Volume | 129 |
Issue number | 2 |
Publication status | Published - 01 Apr 1982 |