COMPLETELY ITERATIVE, PIPELINED MULTIPLIER ARRAY SUITABLE FOR VLSI.

John V. McCanny, John G. McWhirter

Research output: Contribution to journalArticlepeer-review

48 Citations (Scopus)

Abstract

A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described. Attention is focused on a circuit which is used to multiply streams of parallel unsigned data. Then an algorithm is given which demonstrates that, with only a simple modification to the basic cell, the same array can cope with two's complement numbers. The resulting structure has a number of features whch make it attractive to LSI and VLSI. These include regularity and modularity.
Original languageEnglish
Pages (from-to)40-46
Number of pages7
JournalIEE proceedings. Part G. Electronic circuits and systems
Volume129
Issue number2
Publication statusPublished - 01 Apr 1982

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

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