Abstract
An apparatus (1) for implementing a cyclic redundancy check (CRC) error detection methodology to compute a CRC error detection code for data according to the methodology, comprising computation means (2) which uses parallel computation (4) to compute the CRC error detection code, and configurator means (3) which uses the CRC error detection methodology to determine a configuration of the computation means required to compute the CRC error detection code, and configures (25) the computation means accordingly, wherein the configurator means is able to use each of a plurality of CRC error detection methodologies to determine a configuration of the computation means required for parallel computation of a CRC error detection code according to each of the methodologies, and the computation means is configurable to allow configuration thereof for parallel computation of each CRC error detection code.
| Original language | English |
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| Patent number | 8321751 |
| IPC | US8321751 B2 |
| Priority date | 22/04/2006 |
| Publication status | Published - 12 Nov 2012 |