Sphere Decoding (SD) enables real-time quasi-optimal symbol detection for Multiple-Input Multiple-Output (MIMO) communication systems via custom circuit accelerators. Configurable SDs allow accelerator cost to be balanced with detection accuracy for the most constrained MIMO environments, such as power-constrained Internet-of-Things (IoT) scenarios. However this high detection accuracy comes at high accelerator cost. This paper proposes a novel configurable SD which addresses this issue. A Robust Bounded Spanning with Fast Enumeration (R-BSFE) approach employs novel strategies for channel matrix pre-processing and symbol enumeration to maintain quasi-ML accuracy whilst reducing complexity by up to 74%. This enables accelerators for 802.11n on Xilinx FPGA with significantly lower cost and higher throughput. To the best of the authors’ knowledge, the accelerators produced are the highest performance, lowest cost quasi-ML SD accelerators on record.
|Pages (from-to)||2675 - 2687|
|Number of pages||2687|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - 05 Apr 2021|
Bibliographical notePublisher Copyright:
Copyright 2021 Elsevier B.V., All rights reserved.
- Field programmable gate array (FPGA)
- multiple-input multiple-output (MIMO)
- sphere decoder
ASJC Scopus subject areas
- Electrical and Electronic Engineering