An application specific programmable processor (ASIP) suitable for the real-time implementation of matrix computations such as Singular Value and QR Decomposition is presented. The processor incorporates facilities for the issue of parallel instructions and a dual-bus architecture that are designed to achieve high performance. Internally, it uses a CORDIC module to perform arithmetic operations, with pipelining of the internal recursive loop exploited to multiplex the two independent micro-rotations onto a single piece of hardware. The net result is a flexible processing element whose functionality can be changed under program control, which combines high performance with efficient silicon implementation. This is illustrated through the results of a detailed silicon design study and the applications of the techniques to a combined SVD/QRD system.
|Number of pages||5|
|Journal||Conference Record of the Asilomar Conference on Signals, Systems and Computers|
|Publication status||Published - Nov 2003|
|Event||Asilomar Conference on Signals, Systems & Computers - Pacific Grove, California, United States|
Duration: 01 Nov 2003 → 01 Nov 2003
Bibliographical noteCopyright 2008 Elsevier B.V., All rights reserved.
ASJC Scopus subject areas
- Hardware and Architecture
- Signal Processing
- Electrical and Electronic Engineering