Cross Architectural Power Modelling

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Abstract

Existing power modelling research focuses on the model rather than the process for developing models. An automated power modelling process that can be deployed on different processors for developing power models with high accuracy is developed. For this, (i) an automated hardware performance counter selection method that selects counters best correlated to power on both ARM and Intel processors, (ii) a noise filter based on clustering that can reduce the mean error in power models, and (iii) a two stage power model that surmounts challenges in using existing power models across multiple architectures are proposed and developed. The key results are: (i) the automated hardware performance counter selection method achieves comparable selection to the manual method reported in the literature, (ii) the noise filter reduces the mean error in power models by up to 55%, and (iii) the two stage power model can predict dynamic power with less than 8% error on both ARM and Intel processors, which is an improvement over classic models.
Original languageEnglish
Title of host publication20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing 11/05/2020 → 14/05/2020 Melbourne, Australia
Publisher IEEE
Number of pages10
ISBN (Electronic)978-1-7281-6095-5
DOIs
Publication statusEarly online date - 14 Jul 2020
Event20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing - The Langham, Melbourne, Australia
Duration: 11 May 202014 May 2020
http://cloudbus.org/ccgrid2020/

Conference

Conference20th IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing
Abbreviated titleIEEE/ACM CCGrid
CountryAustralia
CityMelbourne
Period11/05/202014/05/2020
Internet address

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