Dataflow-based design methodology for DSP SoC systems

Silicon technology is still evolving at a remarkable pace and it is highlighted an increasing need to revolutionise design methods for complex DSP systems. One evolution has been the creation of "silicon intellectual" property cores for the realisation of complex systems functions such as MPEG encoders, speech compression and encryption/decryption engines. Whilst this has addressed the creation of some system functionality, it has placed constraints on system level tools where in effect, some of the functionality has been determined in a bottom-up rather than top-down fashion. However, it is essential that any design methodology must be able to take advantage of the availability of these cores. The interest in using dataflow representations to represent and design complex systems at a high level has grown over the past number of years. Whilst tools are starting to emerge to allow mapping of dataflow representations into multi-processor SoC platforms, the ability to develop dedicated hardware implementations and most importantly, utilise existing IP cores in the process, has been presented. The talk presents work carried out in developing a complete dataflow design methodology that allows implementation on SoC platforms comprised of multi-processors and FPGA components. It will be shown how optimisation can be carried out efficiently at the DFG level using silicon IP cores and highlights new levels of programmability needed in IP cores. A number of complex examples will be demonstrated.