With security and surveillance, there is an increasing need to be able to process image data efficiently and effectively either at source or in a large data networks. Whilst Field Programmable Gate Arrays have been seen as a key technology for enabling this, they typically use high level and/or hardware description language synthesis approaches; this provides a major disadvantage in terms of the time needed to design or program them and to verify correct operation; it considerably reduces the programmability capability of any technique based on this technology. The work here proposes a different approach of using optimised soft-core processors which can be programmed in software. In particular, the paper proposes a design tool chain for programming such processors that uses the CAL Actor Language as a starting point for describing an image processing algorithm and targets its implementation to these custom designed, soft-core processors on FPGA. The main purpose is to exploit the task and data parallelism in order to achieve the same parallelism as a previous HDL implementation but avoiding the design time, verification and debugging steps associated with such approaches.
|Title of host publication||2014 48th Asilomar Conference on Signals, Systems and Computers. Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||5|
|Publication status||Published - 27 Apr 2014|
|Event||48th IEEE Asilomar conference on Signal, Systems and Computers - , United States|
Duration: 02 Nov 2014 → 05 Nov 2014
|Conference||48th IEEE Asilomar conference on Signal, Systems and Computers|
|Period||02/11/2014 → 05/11/2014|
ASJC Scopus subject areas
- Computer Networks and Communications
- Signal Processing
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Siddiqui, F. M., 11 Sep 2018
Supervisor: Woods, R. (Supervisor)
Student thesis: Doctoral Thesis › Doctor of PhilosophyFile