Design and analysis of dual-rail circuits for security applications

Danil Sokolov, Julian Murphy, Alex Bystrov, Alex Yakovlev

Research output: Contribution to journalArticlepeer-review

103 Citations (Scopus)


Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.
Original languageEnglish
Pages (from-to)449-460
Number of pages11
JournalIEEE Transactions on Computers
Issue number4
Publication statusPublished - Apr 2005


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