TY - CHAP
T1 - Design and analysis of matching circuit architectures for a closest match lookup
AU - McLaughlin, K.
AU - Sezer, S.
AU - McCanny, J.
AU - Kupzog, F.
AU - Blume, H.
AU - Noll, T.
PY - 2006/1/1
Y1 - 2006/1/1
N2 - This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.
AB - This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.
UR - http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-33847167641&md5=f8852c502d770f0d2f9e7e06887581e1
U2 - 10.1109/IPDPS.2006.1639481
DO - 10.1109/IPDPS.2006.1639481
M3 - Other chapter contribution
AN - SCOPUS:33847167641
VL - 2006
BT - 20th International Parallel and Distributed Processing Symposium, IPDPS 2006
ER -