Design and analysis of matching circuit architectures for a closest match lookup

K. McLaughlin, S. Sezer, J. McCanny, F. Kupzog, H. Blume, T. Noll

Research output: Chapter in Book/Report/Conference proceedingOther chapter contribution

1 Citation (Scopus)

Abstract

This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.
Original languageEnglish
Title of host publication20th International Parallel and Distributed Processing Symposium, IPDPS 2006
Volume2006
DOIs
Publication statusPublished - 01 Jan 2006

ASJC Scopus subject areas

  • Engineering(all)

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