This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.
|Title of host publication||20th International Parallel and Distributed Processing Symposium, IPDPS 2006|
|Publication status||Published - 01 Jan 2006|
ASJC Scopus subject areas