Design and implementation of a field programmable CRC circuit architecture

Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Xin Yang

Research output: Contribution to journalArticle

18 Citations (Scopus)
4 Downloads (Pure)

Abstract

The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s. © 2006 IEEE.
Original languageEnglish
Article number5075525
Pages (from-to)1142-1147
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume17
Issue number8
DOIs
Publication statusPublished - Aug 2009

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Hardware and Architecture
  • Software

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