Design and test of a bit parallel 2nd order IIR filter structure

O.C. McNally, W.P. Marnane, J.V. McCanny

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Test procedures for a pipelined bit-parallel IIR filter chip which maximally exploit its regularity are described. It is shown that small modifications to the basic architecture result in significant reductions in the number of test patterns required to test such chips. The methods used allow 100% fault coverage to be achieved using less than 1000 test vectors for a chip which has 12 bit data and coefficients.
Original languageEnglish
Title of host publicationProceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing
Place of PublicationNEW YORK
PublisherAshgate Publishing
Pages1189-1192
Number of pages4
Volume2
ISBN (Print)0-7803-0003-3
Publication statusPublished - 01 Jan 1991
Event1991 INTERNATIONAL CONF ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING ( ICASSP 91 ) - TORONTO, Canada
Duration: 14 May 199117 May 1991

Conference

Conference1991 INTERNATIONAL CONF ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING ( ICASSP 91 )
CountryCanada
CityTORONTO
Period14/05/199117/05/1991

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