Abstract
Test procedures for a pipelined bit-parallel IIR filter chip which maximally exploit its regularity are described. It is shown that small modifications to the basic architecture result in significant reductions in the number of test patterns required to test such chips. The methods used allow 100% fault coverage to be achieved using less than 1000 test vectors for a chip which has 12 bit data and coefficients.
Original language | English |
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Title of host publication | Proceedings - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing |
Place of Publication | NEW YORK |
Publisher | Ashgate Publishing |
Pages | 1189-1192 |
Number of pages | 4 |
Volume | 2 |
ISBN (Print) | 0-7803-0003-3 |
Publication status | Published - 01 Jan 1991 |
Event | 1991 INTERNATIONAL CONF ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING ( ICASSP 91 ) - TORONTO, Canada Duration: 14 May 1991 → 17 May 1991 |
Conference
Conference | 1991 INTERNATIONAL CONF ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING ( ICASSP 91 ) |
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Country | Canada |
City | TORONTO |
Period | 14/05/1991 → 17/05/1991 |