Design flow for efficient FPGA reconfiguration

Richard Turner, Roger Woods

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

In Run Time Reconfiguration (RTR) systems, the amount of reconfiguration is considerable when compared to the circuit changes implemented. This is because reconfiguration is not considered as part of the design flow. This paper presents a method for reconfigurable circuit design by modeling the underlying FPGA reconfigurable circuitry and taking it into consideration in the system design. This is demonstrated for an image processing example on the Xilinx Virtex FPGA.
Original languageEnglish
Pages (from-to)972-975
Number of pages4
JournalFIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS
Volume2778
Publication statusPublished - 2003

ASJC Scopus subject areas

  • Biochemistry, Genetics and Molecular Biology(all)
  • Computer Science(all)
  • Theoretical Computer Science

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