In Run Time Reconfiguration (RTR) systems, the amount of reconfiguration is considerable when compared to the circuit changes implemented. This is because reconfiguration is not considered as part of the design flow. This paper presents a method for reconfigurable circuit design by modeling the underlying FPGA reconfigurable circuitry and taking it into consideration in the system design. This is demonstrated for an image processing example on the Xilinx Virtex FPGA.
|Number of pages||4|
|Journal||FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS|
|Publication status||Published - 2003|
ASJC Scopus subject areas
- Biochemistry, Genetics and Molecular Biology(all)
- Computer Science(all)
- Theoretical Computer Science