TY - GEN
T1 - Design methodology for a block motion estimation IP core
AU - Turner, R. H.
AU - Woods, R.
AU - Fischaber, S.
AU - McAllister, J.
PY - 2008/9/22
Y1 - 2008/9/22
N2 - APT, Whiterock Business Park, 729 Springfield Road, Belfast, N. Ireland The paper describes the design of a parameterizable core for motion estimation. Using a high level strategy targeted at memory requirements, a core has been developed for H.261, H.263 and MPEG-2 video compression standards which works efficiently across a range of search mechanisms, window sizes and error metrics. The core can perform motion estimation at up to 150 frame/s and performs well across the parameter range, demonstrating the design quality.
AB - APT, Whiterock Business Park, 729 Springfield Road, Belfast, N. Ireland The paper describes the design of a parameterizable core for motion estimation. Using a high level strategy targeted at memory requirements, a core has been developed for H.261, H.263 and MPEG-2 video compression standards which works efficiently across a range of search mechanisms, window sizes and error metrics. The core can perform motion estimation at up to 150 frame/s and performs well across the parameter range, demonstrating the design quality.
KW - FPGA
KW - IP cores
KW - Motion estimation
UR - http://www.scopus.com/inward/record.url?scp=51849102805&partnerID=8YFLogxK
U2 - 10.1109/ICNNSP.2008.4590443
DO - 10.1109/ICNNSP.2008.4590443
M3 - Conference contribution
AN - SCOPUS:51849102805
SN - 9781424423118
T3 - 2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP
SP - 711
EP - 716
BT - 2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP
T2 - 2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP
Y2 - 7 June 2008 through 11 June 2008
ER -