Design methodology for a block motion estimation IP core

R. H. Turner, R. Woods, S. Fischaber, J. McAllister

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

APT, Whiterock Business Park, 729 Springfield Road, Belfast, N. Ireland The paper describes the design of a parameterizable core for motion estimation. Using a high level strategy targeted at memory requirements, a core has been developed for H.261, H.263 and MPEG-2 video compression standards which works efficiently across a range of search mechanisms, window sizes and error metrics. The core can perform motion estimation at up to 150 frame/s and performs well across the parameter range, demonstrating the design quality.

Original languageEnglish
Title of host publication2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP
Pages711-716
Number of pages6
DOIs
Publication statusPublished - 22 Sep 2008
Event2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP - Zhenjiang, China
Duration: 07 Jun 200811 Jun 2008

Publication series

Name2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP

Conference

Conference2008 IEEE International Conference Neural Networks and Signal Processing, ICNNSP
CountryChina
CityZhenjiang
Period07/06/200811/06/2008

Keywords

  • FPGA
  • IP cores
  • Motion estimation

ASJC Scopus subject areas

  • Artificial Intelligence
  • Signal Processing

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