Design methodology to trade off power, output quality and error resiliency: Application to color interpolation filtering

Georgios Karakonstantis*, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Abstract

Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in. sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.

Original languageEnglish
Title of host publicationIEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2
Place of PublicationNEW YORK
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages199-204
Number of pages6
ISBN (Print)978-1-4244-1381-2
Publication statusPublished - 2007
EventIEEE/ACM International Conference on Computer-Aided Design - San Jose, Canada
Duration: 04 Nov 200708 Nov 2007

Publication series

NameIEEE INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN
PublisherIEEE
ISSN (Print)1063-6757

Conference

ConferenceIEEE/ACM International Conference on Computer-Aided Design
CountryCanada
Period04/11/200708/11/2007

Keywords

  • ARRAY INTERPOLATION
  • DEMOSAICKING

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