Design of interlock-free combined allocators for Networks-on-Chip

Ye Lu; Changlin Chen; John Vincent  McCanny; Sakir  Sezer

doi:10.1109/SOCC.2012.6398332

Design of interlock-free combined allocators for Networks-on-Chip

Ye Lu, Changlin Chen, John Vincent McCanny, Sakir Sezer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Citations (Scopus)

Abstract

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

Original language	English
Title of host publication	IEEE International SOC Conference (SOCC), 2012
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	358 - 363
Number of pages	6
DOIs	https://doi.org/10.1109/SOCC.2012.6398332
Publication status	Published - 2012

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering
Electrical and Electronic Engineering

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10.1109/SOCC.2012.6398332

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@inproceedings{4b9763a0f3fc42e0bdaaaa15ca30c167,

title = "Design of interlock-free combined allocators for Networks-on-Chip",

abstract = "This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology. ",

author = "Ye Lu and Changlin Chen and McCanny, {John Vincent} and Sakir Sezer",

year = "2012",

doi = "10.1109/SOCC.2012.6398332",

language = "English",

pages = "358 -- 363",

booktitle = "IEEE International SOC Conference (SOCC), 2012",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

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AU - Lu, Ye

AU - Chen, Changlin

AU - McCanny, John Vincent

AU - Sezer, Sakir

PY - 2012

Y1 - 2012

N2 - This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

AB - This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.

U2 - 10.1109/SOCC.2012.6398332

DO - 10.1109/SOCC.2012.6398332

M3 - Conference contribution

SP - 358

EP - 363

BT - IEEE International SOC Conference (SOCC), 2012

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Design of interlock-free combined allocators for Networks-on-Chip

Abstract

ASJC Scopus subject areas

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