Design of interlock-free combined allocators for Networks-on-Chip

Ye Lu, Changlin Chen, John Vincent McCanny, Sakir Sezer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

This paper presents a thorough investigation of the combined allocator design for Networks-on-Chip (NoC). Particularly, we discuss the interlock of the combined NoC allocator, which is caused by the lock mechanism of priority updating between the local and global arbiters. Architectures and implementations of three interlock-free combined allocators are presented in detail. Their cost, critical path, as well as network level performance are demonstrated based on 65-nm standard cell technology.
Original languageEnglish
Title of host publicationIEEE International SOC Conference (SOCC), 2012
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages358 - 363
Number of pages6
DOIs
Publication statusPublished - 2012

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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  • Cite this

    Lu, Y., Chen, C., McCanny, J. V., & Sezer, S. (2012). Design of interlock-free combined allocators for Networks-on-Chip. In IEEE International SOC Conference (SOCC), 2012 (pp. 358 - 363). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/SOCC.2012.6398332