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Abstract
The C-element logic gate is a key component for constructing asynchronous control in silicon integrated circuits. The purpose of this reported work is to introduce a new speed-independent C-element design, which is synthesised by the asynchronous Petrify design tool to ensure it is composed of sequential digital latches rather than complex gates. The benefits are that it guarantees correct speed-independent operation, together with easy integration in modern design flows and processes. It is compared to an equivalent speed-independent complex gate C-element design generated by Petrify in a 130 nm semiconductor process.
Original language | English |
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Pages (from-to) | 1190-1191 |
Number of pages | 2 |
Journal | IET Electronic Letters |
Volume | 48 |
Issue number | 19 |
DOIs | |
Publication status | Published - Sep 2012 |
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Dive into the research topics of 'Design of latch-based C-element'. Together they form a unique fingerprint.Projects
- 1 Finished
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R1118ECI: Centre for Secure Information Technologies (CSIT)
McCanny, J. V., Cowan, C., Crookes, D., Fusco, V., Linton, D., Liu, W., Miller, P., O'Neill, M., Scanlon, W. & Sezer, S.
01/08/2009 → 30/06/2014
Project: Research