Analysis and synthesis of the new Class-EF power amplifier (PA) are presented in this paper. The proposed circuit offers means to alleviate some of the major issues faced by existing Class-EF and Class-EF PAs, such as (1) substantial power losses due to parasitic resistance of the large inductor in the Class-EF load network, (2) unpredictable behaviour of practical lumped inductors and capacitors at harmonic frequencies, and (3) deviation from ideal Class-EF operation mode due to detrimental effects of device output inductance at high frequencies. The transmission-line load network of the Class-EF PA topology elaborated in this paper simultaneously satisfies the Class-EF optimum impedance requirements at fundamental frequency, second, and third harmonics as well as simultaneously providing matching to the circuit optimum load resistance for any prescribed system load resistance. Furthermore, an elegant solution using an open and short-circuit stub arrangement is suggested to overcome the problem encountered in the mm-wave IC realizations of the Class-EF PA load network due to lossy quarter-wave line.
|Number of pages||4|
|Publication status||Published - Dec 2010|
|Event||Asia-Pacific Microwave Conference - Yokohama, Japan|
Duration: 01 Dec 2010 → 01 Dec 2010
|Conference||Asia-Pacific Microwave Conference|
|Period||01/12/2010 → 01/12/2010|
Thian, M., & Fusco, V. (2010). Design technique for mm-wave IC realization of the load network of switched-mode class-EF power amplifier. 402-405. Paper presented at Asia-Pacific Microwave Conference, Yokohama, Japan. http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5728644&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5728644