Designing high-throughput hardware accelerator for stream cipher HC-128

Anupam Chattopadhyay; Ayesha Khalid; Subhamoy Maitra; Shashwat Raizada

doi:10.1109/ISCAS.2012.6271518

Designing high-throughput hardware accelerator for stream cipher HC-128

Anupam Chattopadhyay^*, Ayesha Khalid, Subhamoy Maitra, Shashwat Raizada

^*Corresponding author for this work

Institute of Electronics, Communications & Information Technology

Research output: Contribution to conference › Paper › peer-review

8 Citations (Scopus)

Abstract

Due to ubiquitous deployment of embedded systems, security and privacy are emerging as major design concerns and new stream ciphers are being proposed by the cryptographic community. HC-128 is one of the recent stream ciphers that received attention after its selection as an eStream candidate. Till date, the cipher is believed to have a good security margin. In this paper we study several implementation issues for HC-128 in a disciplined manner. We first discuss the experience on embedded and customizable processors. Then we consider a dedicated hardware accelerator implementation. Further we explore several parallelization strategies for improving throughput. To the best of our knowledge such a detailed implementation exercise has not been presented in the literature. Our novel implementation strategies mark the fastest HC-128 execution reported till date.

Original language	English
Pages	1448-1451
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2012.6271518
Publication status	Published - 28 Sept 2012
Event	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of Duration: 20 May 2012 → 23 May 2012

Conference

Conference	2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/Territory	Korea, Republic of
City	Seoul
Period	20/05/2012 → 23/05/2012

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ISCAS.2012.6271518

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abstract = "Due to ubiquitous deployment of embedded systems, security and privacy are emerging as major design concerns and new stream ciphers are being proposed by the cryptographic community. HC-128 is one of the recent stream ciphers that received attention after its selection as an eStream candidate. Till date, the cipher is believed to have a good security margin. In this paper we study several implementation issues for HC-128 in a disciplined manner. We first discuss the experience on embedded and customizable processors. Then we consider a dedicated hardware accelerator implementation. Further we explore several parallelization strategies for improving throughput. To the best of our knowledge such a detailed implementation exercise has not been presented in the literature. Our novel implementation strategies mark the fastest HC-128 execution reported till date.",

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AU - Raizada, Shashwat

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AB - Due to ubiquitous deployment of embedded systems, security and privacy are emerging as major design concerns and new stream ciphers are being proposed by the cryptographic community. HC-128 is one of the recent stream ciphers that received attention after its selection as an eStream candidate. Till date, the cipher is believed to have a good security margin. In this paper we study several implementation issues for HC-128 in a disciplined manner. We first discuss the experience on embedded and customizable processors. Then we consider a dedicated hardware accelerator implementation. Further we explore several parallelization strategies for improving throughput. To the best of our knowledge such a detailed implementation exercise has not been presented in the literature. Our novel implementation strategies mark the fastest HC-128 execution reported till date.

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Designing high-throughput hardware accelerator for stream cipher HC-128

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