Abstract
A generator for the automated design of Discrete Cosine Transform (DCT) cores is presented. This can be used to rapidly create silicon circuits from a high level specification. These compare very favourably with existing designs. The DCT cores produced are scaleable in terms of point size as well as input/output and coefficient wordlengths. This provides a high degree of flexibility. An example, 8-point 1D DCT design, produced occupies less than 0.92 mm when implemented in a 0.35µ double level metal CMOS technology. This can be clocked at a rate of 100MHz.
Original language | English |
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Pages (from-to) | 2997-3000 |
Number of pages | 4 |
Journal | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |
Volume | 5 |
Publication status | Published - 01 Jan 1998 |
Bibliographical note
Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering
- Acoustics and Ultrasonics