Discrete cosine transform generator for VLSI synthesis

Jill Hunter; John V. McCanny

Discrete cosine transform generator for VLSI synthesis

Jill Hunter
, John V. McCanny

Research output: Contribution to journal › Article › peer-review

Abstract

A generator for the automated design of Discrete Cosine Transform (DCT) cores is presented. This can be used to rapidly create silicon circuits from a high level specification. These compare very favourably with existing designs. The DCT cores produced are scaleable in terms of point size as well as input/output and coefficient wordlengths. This provides a high degree of flexibility. An example, 8-point 1D DCT design, produced occupies less than 0.92 mm when implemented in a 0.35µ double level metal CMOS technology. This can be clocked at a rate of 100MHz.

Original language	English
Pages (from-to)	2997-3000
Number of pages	4
Journal	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume	5
Publication status	Published - 01 Jan 1998

Bibliographical note

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering
Acoustics and Ultrasonics

Cite this

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title = "Discrete cosine transform generator for VLSI synthesis",

abstract = "A generator for the automated design of Discrete Cosine Transform (DCT) cores is presented. This can be used to rapidly create silicon circuits from a high level specification. These compare very favourably with existing designs. The DCT cores produced are scaleable in terms of point size as well as input/output and coefficient wordlengths. This provides a high degree of flexibility. An example, 8-point 1D DCT design, produced occupies less than 0.92 mm when implemented in a 0.35µ double level metal CMOS technology. This can be clocked at a rate of 100MHz.",

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AB - A generator for the automated design of Discrete Cosine Transform (DCT) cores is presented. This can be used to rapidly create silicon circuits from a high level specification. These compare very favourably with existing designs. The DCT cores produced are scaleable in terms of point size as well as input/output and coefficient wordlengths. This provides a high degree of flexibility. An example, 8-point 1D DCT design, produced occupies less than 0.92 mm when implemented in a 0.35µ double level metal CMOS technology. This can be clocked at a rate of 100MHz.

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SN - 0736-7791

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JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

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ER -

Discrete cosine transform generator for VLSI synthesis

Abstract

Bibliographical note

ASJC Scopus subject areas

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Cite this