Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators

Safiullah Khan; Ayesha Khalid; Ciara Rafferty; Yasir Shah; Maire O'Neill; Wai Kong Lee; Seong Oun Hwang

doi:10.1109/VLSI-SoC57769.2023.10321885

Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators

Safiullah Khan^*, Ayesha Khalid, Ciara Rafferty, Yasir Shah, Maire O'Neill^*, Wai Kong Lee^*, Seong Oun Hwang

^*Corresponding author for this work

School of Electronics, Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

149 Downloads (Pure)

Abstract

The dawn of cost-effective miniaturised satellites is currently attracting venture capital in a never seen before ratio to launch mega-constellations of satellites for a diverse range of applications. These satellites are vulnerable to attacks by high-capability cyber-criminals (including quantum enabled adversaries), due to the critical data they transmit. Additionally, space missions have long lifespan and a long lead time in terms of development process, requiring a pre-emptive outlook to ensuring their safety. In 2016, National Institute of Standards and Technology (NIST) initiated the competition to standardise the post-quantum cryptography (PQC) schemes, announcing the first portfolio of chosen schemes in 2022. This work targets the only public key exchange (PKE) scheme among the winners of the NIST-PQC standardisation process, CRYSTALS-Kyber, and implements its core bottleneck operation, i.e., number theoretic transform (NTT) extensively used for the polynomial multiplication. To avoid data corruption due to space based radiations, a novel error-resistant model for NTT is presented based on hybrid protection mechanisms, i.e., the use of hamming codes for detection and correction of errors in the twiddle factors and the use of parity computed for all NTT coefficients for error detection. Benchmarking error protection overheads on a Xilinx Virtex-7 FPGA reports 16.4% and 10.8% degradation on the hardware efficiency when the hamming codes for twiddle factors and parity bit for NTT coefficients are used to mitigate errors, respectively. A total of 29.2% area overhead is benchmarked when compared to the standard unprotected NTT implementations.

Original language	English
Title of host publication	2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC): proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350325997
ISBN (Print)	9798350326000
DOIs	https://doi.org/10.1109/VLSI-SoC57769.2023.10321885
Publication status	Published - 22 Nov 2023
Event	VLSI-SOC 2023: 31ST IFIP/IEEE CONFERENCE ON VERY LARGE SCALE INTEGRATION - University of Sharjah, Sharjah, United Arab Emirates Duration: 16 Oct 2023 → 18 Oct 2023 https://sites.google.com/view/vlsi-soc2023/home

Publication series

Name	IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC): proceedings
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	VLSI-SOC 2023: 31ST IFIP/IEEE CONFERENCE ON VERY LARGE SCALE INTEGRATION
Abbreviated title	VLSI-SOC
Country/Territory	United Arab Emirates
City	Sharjah
Period	16/10/2023 → 18/10/2023
Internet address	https://sites.google.com/view/vlsi-soc2023/home

Keywords

NTT
PQC
FPGA
cryptography
fault tolerance

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Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators
Copyright 2023 IEEE. This work is made available online in accordance with the publisher’s policies. Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 546 KBLicence: Unspecified

Cite this

Khan, S., Khalid, A., Rafferty, C., Shah, Y., O'Neill, M., Lee, W. K., & Hwang, S. O. (2023). Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators. In 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC): proceedings (IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC): proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-SoC57769.2023.10321885

Khan, Safiullah ; Khalid, Ayesha ; Rafferty, Ciara et al. / Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators. 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC): proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC): proceedings).

@inproceedings{84d50dae27c44c2d886219ad44f38d90,

title = "Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators",

abstract = "The dawn of cost-effective miniaturised satellites is currently attracting venture capital in a never seen before ratio to launch mega-constellations of satellites for a diverse range of applications. These satellites are vulnerable to attacks by high-capability cyber-criminals (including quantum enabled adversaries), due to the critical data they transmit. Additionally, space missions have long lifespan and a long lead time in terms of development process, requiring a pre-emptive outlook to ensuring their safety. In 2016, National Institute of Standards and Technology (NIST) initiated the competition to standardise the post-quantum cryptography (PQC) schemes, announcing the first portfolio of chosen schemes in 2022. This work targets the only public key exchange (PKE) scheme among the winners of the NIST-PQC standardisation process, CRYSTALS-Kyber, and implements its core bottleneck operation, i.e., number theoretic transform (NTT) extensively used for the polynomial multiplication. To avoid data corruption due to space based radiations, a novel error-resistant model for NTT is presented based on hybrid protection mechanisms, i.e., the use of hamming codes for detection and correction of errors in the twiddle factors and the use of parity computed for all NTT coefficients for error detection. Benchmarking error protection overheads on a Xilinx Virtex-7 FPGA reports 16.4% and 10.8% degradation on the hardware efficiency when the hamming codes for twiddle factors and parity bit for NTT coefficients are used to mitigate errors, respectively. A total of 29.2% area overhead is benchmarked when compared to the standard unprotected NTT implementations.",

keywords = "NTT, PQC, FPGA, cryptography, fault tolerance",

author = "Safiullah Khan and Ayesha Khalid and Ciara Rafferty and Yasir Shah and Maire O'Neill and Lee, {Wai Kong} and Hwang, {Seong Oun}",

year = "2023",

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language = "English",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC): proceedings",

address = "United States",

note = "<br/> <br/>VLSI-SOC 2023: 31ST IFIP/IEEE CONFERENCE ON VERY LARGE SCALE INTEGRATION, VLSI-SOC ; Conference date: 16-10-2023 Through 18-10-2023",

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Khan, S, Khalid, A , Rafferty, C, Shah, Y, O'Neill, M, Lee, WK & Hwang, SO 2023, Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators. in 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC): proceedings. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC): proceedings, Institute of Electrical and Electronics Engineers Inc.,

VLSI-SOC 2023: 31ST IFIP/IEEE CONFERENCE ON VERY LARGE SCALE INTEGRATION, Sharjah, United Arab Emirates, 16/10/2023. https://doi.org/10.1109/VLSI-SoC57769.2023.10321885

Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators. / Khan, Safiullah; Khalid, Ayesha ; Rafferty, Ciara et al.
2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC): proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC): proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators

AU - Khan, Safiullah

AU - Khalid, Ayesha

AU - Rafferty, Ciara

AU - Shah, Yasir

AU - O'Neill, Maire

AU - Lee, Wai Kong

AU - Hwang, Seong Oun

PY - 2023/11/22

Y1 - 2023/11/22

N2 - The dawn of cost-effective miniaturised satellites is currently attracting venture capital in a never seen before ratio to launch mega-constellations of satellites for a diverse range of applications. These satellites are vulnerable to attacks by high-capability cyber-criminals (including quantum enabled adversaries), due to the critical data they transmit. Additionally, space missions have long lifespan and a long lead time in terms of development process, requiring a pre-emptive outlook to ensuring their safety. In 2016, National Institute of Standards and Technology (NIST) initiated the competition to standardise the post-quantum cryptography (PQC) schemes, announcing the first portfolio of chosen schemes in 2022. This work targets the only public key exchange (PKE) scheme among the winners of the NIST-PQC standardisation process, CRYSTALS-Kyber, and implements its core bottleneck operation, i.e., number theoretic transform (NTT) extensively used for the polynomial multiplication. To avoid data corruption due to space based radiations, a novel error-resistant model for NTT is presented based on hybrid protection mechanisms, i.e., the use of hamming codes for detection and correction of errors in the twiddle factors and the use of parity computed for all NTT coefficients for error detection. Benchmarking error protection overheads on a Xilinx Virtex-7 FPGA reports 16.4% and 10.8% degradation on the hardware efficiency when the hamming codes for twiddle factors and parity bit for NTT coefficients are used to mitigate errors, respectively. A total of 29.2% area overhead is benchmarked when compared to the standard unprotected NTT implementations.

AB - The dawn of cost-effective miniaturised satellites is currently attracting venture capital in a never seen before ratio to launch mega-constellations of satellites for a diverse range of applications. These satellites are vulnerable to attacks by high-capability cyber-criminals (including quantum enabled adversaries), due to the critical data they transmit. Additionally, space missions have long lifespan and a long lead time in terms of development process, requiring a pre-emptive outlook to ensuring their safety. In 2016, National Institute of Standards and Technology (NIST) initiated the competition to standardise the post-quantum cryptography (PQC) schemes, announcing the first portfolio of chosen schemes in 2022. This work targets the only public key exchange (PKE) scheme among the winners of the NIST-PQC standardisation process, CRYSTALS-Kyber, and implements its core bottleneck operation, i.e., number theoretic transform (NTT) extensively used for the polynomial multiplication. To avoid data corruption due to space based radiations, a novel error-resistant model for NTT is presented based on hybrid protection mechanisms, i.e., the use of hamming codes for detection and correction of errors in the twiddle factors and the use of parity computed for all NTT coefficients for error detection. Benchmarking error protection overheads on a Xilinx Virtex-7 FPGA reports 16.4% and 10.8% degradation on the hardware efficiency when the hamming codes for twiddle factors and parity bit for NTT coefficients are used to mitigate errors, respectively. A total of 29.2% area overhead is benchmarked when compared to the standard unprotected NTT implementations.

KW - NTT

KW - PQC

KW - FPGA

KW - cryptography

KW - fault tolerance

U2 - 10.1109/VLSI-SoC57769.2023.10321885

DO - 10.1109/VLSI-SoC57769.2023.10321885

M3 - Conference contribution

SN - 9798350326000

T3 - IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC): proceedings

BT - 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC): proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - <br/> <br/>VLSI-SOC 2023: 31ST IFIP/IEEE CONFERENCE ON VERY LARGE SCALE INTEGRATION

Y2 - 16 October 2023 through 18 October 2023

ER -

Khan S, Khalid A , Rafferty C, Shah Y, O'Neill M, Lee WK et al. Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators. In 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC): proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC): proceedings). doi: 10.1109/VLSI-SoC57769.2023.10321885

Efficient, error-resistant NTT architectures for CRYSTALS-Kyber FPGA accelerators

Abstract

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Conference

Keywords

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