The class of moduli sets in the form of 2k,2n-1,2n+1,m4 with m42r+1,2r-1 has earned significant popularity in the implementation of the Residue Number System (RNS)-based computational systems, mainly thanks to the efficient arithmetic unit and a high degree of parallelism. However, its complicated inter-modulo computation leads to a high overhead associated with the complex reverse converter. This overhead is the main barrier for energy-efficient implementation of RNS-based devices, particularly for edge computing applications. This brief presents a new approach that embeds the reverse converter into the arithmetic unit of the RNS processor for the aforesaid well-known class of moduli sets. The effective hardware reuse in the proposed approach leads to an area and energy-efficient RNS realization for this class of moduli set. The experimental results based on 65 nm CMOS technology indicate the superiority of RNS realization by employing the proposed design methodology. The proposed architecture for a given RNS provides a substantial 17.4% area-saving and 13.32% less power-consumption on average compared to the traditional design approach, with the negligible penalty in delay.
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Early online date||16 Oct 2020|
|Publication status||Early online date - 16 Oct 2020|
- Residue Number System
- Arithmetic Unit
ASJC Scopus subject areas
- Hardware and Architecture