Efficient Incorporation of the RNS DataPath in Reverse Converter

MohammadReza Taheri, Amir Sabbagh Molahosseini, Keivan Navi*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)
119 Downloads (Pure)


The class of moduli sets in the form of 2k,2n-1,2n+1,m4 with m42r+1,2r-1 has earned significant popularity in the implementation of the Residue Number System (RNS)-based computational systems, mainly thanks to the efficient arithmetic unit and a high degree of parallelism. However, its complicated inter-modulo computation leads to a high overhead associated with the complex reverse converter. This overhead is the main barrier for energy-efficient implementation of RNS-based devices, particularly for edge computing applications. This brief presents a new approach that embeds the reverse converter into the arithmetic unit of the RNS processor for the aforesaid well-known class of moduli sets. The effective hardware reuse in the proposed approach leads to an area and energy-efficient RNS realization for this class of moduli set. The experimental results based on 65 nm CMOS technology indicate the superiority of RNS realization by employing the proposed design methodology. The proposed architecture for a given RNS provides a substantial 17.4% area-saving and 13.32% less power-consumption on average compared to the traditional design approach, with the negligible penalty in delay.
Original languageEnglish
Article number9226450
Pages (from-to)1388-1392
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Issue number4
Early online date16 Oct 2020
Publication statusPublished - 01 Apr 2021


  • Residue Number System
  • Arithmetic Unit

ASJC Scopus subject areas

  • Hardware and Architecture


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