Efficient single-chip implementation of SHA-384 and SHA-512

M. McLoone; J. V. McCanny

doi:10.1109/FPT.2002.1188699

Efficient single-chip implementation of SHA-384 and SHA-512

M. McLoone, J. V. McCanny

Queen's University Belfast

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

42 Citations (Scopus)

Abstract

The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature.

Original language	English
Title of host publication	Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	311-314
Number of pages	4
ISBN (Electronic)	0780375742, 9780780375741
DOIs	https://doi.org/10.1109/FPT.2002.1188699
Publication status	Published - 01 Jan 2002
Event	1st IEEE International Conference on FieId-Programmable Technology, FPT 2002 - Hong Kong, Hong Kong Duration: 16 Dec 2002 → 18 Dec 2002

Conference

Conference	1st IEEE International Conference on FieId-Programmable Technology, FPT 2002
Country	Hong Kong
City	Hong Kong
Period	16/12/2002 → 18/12/2002

ASJC Scopus subject areas

Software
Electrical and Electronic Engineering
Hardware and Architecture

Access to Document

10.1109/FPT.2002.1188699

Link to publication in Scopus

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Cite this

@inproceedings{765a9b6ed04a4d1a88fca99d8b7d894d,

title = "Efficient single-chip implementation of SHA-384 and SHA-512",

abstract = "The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature.",

author = "M. McLoone and McCanny, {J. V.}",

year = "2002",

month = jan,

day = "1",

doi = "10.1109/FPT.2002.1188699",

language = "English",

pages = "311--314",

booktitle = "Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "1st IEEE International Conference on FieId-Programmable Technology, FPT 2002 ; Conference date: 16-12-2002 Through 18-12-2002",

}

McLoone, M & McCanny, JV 2002, Efficient single-chip implementation of SHA-384 and SHA-512. in Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002., 1188699, Institute of Electrical and Electronics Engineers Inc., pp. 311-314, 1st IEEE International Conference on FieId-Programmable Technology, FPT 2002, Hong Kong, Hong Kong, 16/12/2002. https://doi.org/10.1109/FPT.2002.1188699

TY - GEN

T1 - Efficient single-chip implementation of SHA-384 and SHA-512

AU - McLoone, M.

AU - McCanny, J. V.

PY - 2002/1/1

Y1 - 2002/1/1

N2 - The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature.

AB - The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature.

UR - http://www.scopus.com/inward/record.url?scp=2442577898&partnerID=8YFLogxK

U2 - 10.1109/FPT.2002.1188699

DO - 10.1109/FPT.2002.1188699

M3 - Conference contribution

AN - SCOPUS:2442577898

SP - 311

EP - 314

BT - Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1st IEEE International Conference on FieId-Programmable Technology, FPT 2002

Y2 - 16 December 2002 through 18 December 2002

ER -