Abstract
The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature.
Original language | English |
---|---|
Title of host publication | Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 311-314 |
Number of pages | 4 |
ISBN (Electronic) | 0780375742, 9780780375741 |
DOIs | |
Publication status | Published - 01 Jan 2002 |
Event | 1st IEEE International Conference on FieId-Programmable Technology, FPT 2002 - Hong Kong, Hong Kong Duration: 16 Dec 2002 → 18 Dec 2002 |
Conference
Conference | 1st IEEE International Conference on FieId-Programmable Technology, FPT 2002 |
---|---|
Country | Hong Kong |
City | Hong Kong |
Period | 16/12/2002 → 18/12/2002 |
ASJC Scopus subject areas
- Software
- Electrical and Electronic Engineering
- Hardware and Architecture