Efficient single-chip implementation of SHA-384 and SHA-512

Research output: Chapter in Book/Report/Conference proceedingConference contribution

41 Citations (Scopus)

Abstract

The rapid developments in the communications industry over the last decade have led to an escalation in the amount of sensitive data being transmitted over the Internet. This has resulted in an increased awareness of the need to provide security measures. Authentication is one such security measure. A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms is described in this paper. The compact implementation achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs). This is believed to be the first SHA-384/SHA-512 hardware implementation to be reported in the literature.

Original languageEnglish
Title of host publicationProceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages311-314
Number of pages4
ISBN (Electronic)0780375742, 9780780375741
DOIs
Publication statusPublished - 01 Jan 2002
Event1st IEEE International Conference on FieId-Programmable Technology, FPT 2002 - Hong Kong, Hong Kong
Duration: 16 Dec 200218 Dec 2002

Conference

Conference1st IEEE International Conference on FieId-Programmable Technology, FPT 2002
CountryHong Kong
CityHong Kong
Period16/12/200218/12/2002

ASJC Scopus subject areas

  • Software
  • Electrical and Electronic Engineering
  • Hardware and Architecture

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    McLoone, M., & McCanny, J. V. (2002). Efficient single-chip implementation of SHA-384 and SHA-512. In Proceedings - 2002 IEEE International Conference on FieId-Programmable Technology, FPT 2002 (pp. 311-314). [1188699] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPT.2002.1188699