Electrical Characterisation of SOI Substrates Incorporating WSix Ground Planes

Michael Bain, M. Jin, S. Loh, Mervyn Armstrong, Harold Gamble, David McNeill

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of similar to 0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.
Original languageEnglish
Pages (from-to)72-74
Number of pages3
JournalIEEE Electron Device Letters
Volume26
Issue number2
DOIs
Publication statusPublished - Feb 2005

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