Abstract
Fixed-Complexity Sphere Decoder (FSD) is an quasi-optimal detector for Multiple-Input Multiple-Output (MIMO) system which is a hardware-friendly parallel tree-search customised to the modulation and antenna scheme employed. However, it is not able to adapt its behaviour for various modulation and antenna schemes, as demanded by modern wireless standard. This restricts its usage in modern adaptive MIMO systems. This paper proposes a solution to this problem. A configurable FSD structure in proposed where normalized higher order modulation schemes can accommodate lower ones. By exploiting clock-gating, FSD of all modulation schemes is equally trimmed to allow power savings of over 30% when implementing on Field Programmable Gate Array (FPGA). This architecture enables the facility to balance the power consumptions with compatible information rate in dynamic, adaptive MIMO communications environments.
Original language | English |
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Title of host publication | 2021 IEEE Workshop on Signal Processing Systems (SiPS 2021): Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 82-87 |
Number of pages | 6 |
ISBN (Electronic) | 9781665401449 |
DOIs | |
Publication status | Published - 13 Nov 2021 |
Event | 2021 IEEE Workshop on Signal Processing Systems, SiPS 2021 - Coimbra, Portugal Duration: 19 Oct 2021 → 21 Oct 2021 |
Publication series
Name | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation |
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Volume | 2021-October |
ISSN (Print) | 1520-6130 |
Conference
Conference | 2021 IEEE Workshop on Signal Processing Systems, SiPS 2021 |
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Country/Territory | Portugal |
City | Coimbra |
Period | 19/10/2021 → 21/10/2021 |
Bibliographical note
Publisher Copyright:© 2021 IEEE.
Keywords
- Adaptive Modulation
- Field Programmable Gate Array
- Fixed-complexity Sphere Decoder
- Multiple-Input Multiple-Output
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Signal Processing
- Applied Mathematics
- Hardware and Architecture