This brief presents a new energy efficient Fast- Fourier Transform (FFT) architecture for real-valued applications. The proposed architecture decimates the FFT in time domain with bit-reversed inputs which allows to avoid the use of all costly complex FFTs operations required by the existing schemes. This leads to the reduction of the required memory by a factor of 2 while processing two inputs in parallel, thus doubling the throughput and improving the energy efficiency compared to the current real-valued FFT designs. Furthermore, the output frequencies are computed at their natural order by using a novel memory management technique, without requiring any reordering circuit unlike existing works. In summary for a N point FFT the proposed architecture leads to an increased throughput of 2 samples per clock cycle, requiring N−2 memory cells, 8logN−8 real adders and 3logN−4 real multipliers. Our results show that we can achieve up to 46.86% energy savings when compared with recent real-valued FFT architectures.
|Pages (from-to)||2458 - 2462|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Early online date||30 Mar 2022|
|Publication status||Published - May 2022|