Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories

Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Meinerzhagen, Andreas Burg

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

Current variation aware design methodologies, tuned for worst-case scenarios, are becoming increasingly pessimistic from the perspective of power and performance. A good example of such pessimism is setting the refresh rate of DRAMs according to the worst-case access statistics, thereby resulting in very frequent refresh cycles, which are responsible for the majority of the standby power consumption of these memories. However, such a high refresh rate may not be required, either due to extremely low probability of the actual occurrence of such a worst-case, or due to the inherent error resilient nature of many applications that can tolerate a certain number of potential failures. In this paper, we exploit and quantify the possibilities that exist in dynamic memory design by shifting to the so-called approximate computing paradigm in order to save power and enhance yield at no cost. The statistical characteristics of the retention time in dynamic memories were revealed by studying a fabricated 2kb CMOS compatible embedded DRAM (eDRAM) memory array based on gain-cells. Measurements show that up to 73% of the retention power can be saved by altering the refresh time and setting it such that a small number of failures is allowed. We show that these savings can be further increased by utilizing known circuit techniques, such as body biasing, which can help, not only in extending, but also in preferably shaping the retention time distribution. Our approach is one of the first attempts to access the data integrity and energy tradeoffs achieved in eDRAMs for utilizing them in error resilient applications and can prove helpful in the anticipated shift to approximate computing.

Original languageEnglish
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages489-494
Number of pages6
ISBN (Print)9783981537048, ISSN 1530-1591
Publication statusPublished - 22 Apr 2015
Event2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015 - Grenoble, France
Duration: 09 Mar 201513 Mar 2015

Conference

Conference2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
CountryFrance
CityGrenoble
Period09/03/201513/03/2015

Keywords

  • Data Integrity
  • DRAM
  • Embedded Memories
  • Energy Efficiency
  • Error Resilience
  • Refresh Power

ASJC Scopus subject areas

  • Engineering(all)

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