ePredictNet: low cost error prediction neural network

The pursuit of miniature energy-efficient chips, and push for scaled voltages leads to increased timing errors that threaten the correct system functionality. Conventional error mitigation schemes based on redundancy, require costly and disruptive design changes, while they detect errors after they occur requiring expensive follow up correction schemes. In contrast to existing approaches, this paper introduces ePredictNet, an accurate workload-aware error-predictor based on compressed neural networks that can estimate early error prone instructions and avoid the manifestation of errors even under scaled voltages. Our work shows for the first time that accurate error prediction models are realizable on hardware with very low cost. This is achieved by training a quantized neural network that is converted to a netlist of truth tables using LogicNets, which can efficiently be mapped on circuit. Our results indicate, that ePredictNet once mapped on FPGA can achieve 99.39% error classification accuracy while utilizing only 270 LUTs and comes with only 2.1% area and 5% power overhead once integrated with a RISC core and costs up-to 98% less than the area and power incurred by redundancy based schemes. Apart from a cost effective error estimation scheme, ePredictNet can be used to avoid errors by guiding complimentary error mitigation schemes. For instance, in a power conscious use case, ePredictNet can allow the operation of a Open-RISC core under 12% reduced voltage, allowing to save 17% power with minimal 2.7% throughput reduction and guide the dynamic relaxation of frequency for avoiding errors only once error-prone instructions are predicted.