Error analysis of FFT architectures for digital video applications

Colin C.W. Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper describes how worst-case error analysis can be applied to solve some of the practical issues in the development and implementation of a low power, high performance radix-4 FFT chip for digital video applications. The chip has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W, leading to a cost-effective silicon solution for high quality video processing applications. The analysis focuses on the effect that different radix-4 architectural configurations and finite wordlengths has on the FFT output dynamic range. These issues are addressed using both mathematical error models and through extensive simulation.
Original languageEnglish
Title of host publicationIEEE International Conference on Circuits and Systems
Pages820-823
Number of pages4
Volume2
Publication statusPublished - 01 Jan 1996

Bibliographical note

Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.

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