Evaluating Asymmetric Multicore Systems-on-Chip using Iso-Metrics

Charalambos Chalios, Dimitrios S. Nikolopoulos, Enrique S. Quintana-Orti

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Abstract

The end of Dennard scaling has pushed power consumption into a first order concern for current systems, on par with performance. As a result, near-threshold voltage computing (NTVC) has been proposed as a potential means to tackle the limited cooling capacity of CMOS technology. Hardware operating in NTV consumes significantly less power, at the cost of lower frequency, and thus reduced performance, as well as increased error rates. In this paper, we investigate if a low-power systems-on-chip, consisting of ARM's asymmetric big.LITTLE technology, can be an alternative to conventional high performance multicore processors in terms of power/energy in an unreliable scenario. For our study, we use the Conjugate Gradient solver, an algorithm representative of the computations performed by a large range of scientific and engineering codes.

Original languageEnglish
Number of pages6
Publication statusPublished - 19 Jan 2015
EventHIPEAC Workshop on Energy Efficiency with Heterogeneous Computing (EEHCO 2015) - Amsterdam, Netherlands
Duration: 19 Jan 2015 → …

Conference

ConferenceHIPEAC Workshop on Energy Efficiency with Heterogeneous Computing (EEHCO 2015)
CountryNetherlands
CityAmsterdam
Period19/01/2015 → …

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    Chalios, C., Nikolopoulos, D. S., & Quintana-Orti, E. S. (2015). Evaluating Asymmetric Multicore Systems-on-Chip using Iso-Metrics. Paper presented at HIPEAC Workshop on Energy Efficiency with Heterogeneous Computing (EEHCO 2015), Amsterdam, Netherlands. http://seis.bris.ac.uk/~eejlny/eehco.htm