Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics

Charalambos Chalios, Dimitrios S. Nikolopoulos, Sandra Catalan, Enrique S. Quintana-Orti

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The end of Dennard scaling has promoted low power consumption into a firstorder concern for computing systems. However, conventional power conservation schemes such as voltage and frequency scaling are reaching their limits when used in performance-constrained environments. New technologies are required to break the power wall while sustaining performance on future processors. Low-power embedded processors and near-threshold voltage computing (NTVC) have been proposed as viable solutions to tackle the power wall in future computing systems. Unfortunately, these technologies may also compromise per-core performance and, in the case of NTVC, xreliability. These limitations would make them unsuitable for HPC systems and datacenters. In order to demonstrate that emerging low-power processing technologies can effectively replace conventional technologies, this study relies on ARM’s big.LITTLE processors as both an actual and emulation platform, and state-of-the-art implementations of the CG solver. For NTVC in particular, the paper describes how efficient algorithm-based fault tolerance schemes preserve the power and energy benefits of very low voltage operation.
Original languageEnglish
Pages (from-to)85-92
JournalIET Computers And Digital Techniques
Issue number2
Publication statusPublished - 08 Feb 2016


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