Exploring Technology Related Design-Space Limitations of High Performance Network Processing

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper summarizes numerous research activities in high-performance networks and network security processing, and explores technology related performance constraints such as critical performance limitations of circuit architectures, which are set by the semiconductor technologies.

Original languageEnglish
Title of host publicationESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE
EditorsD SchmittLandsiedel, T Noll
Place of PublicationNEW YORK
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages222-231
Number of pages10
ISBN (Print)978-1-4244-1125-2
Publication statusPublished - Sep 2007
EventIEEE European Solid State Circuits Conference (ESSCIRC) - Munich, Germany
Duration: 01 Sep 200701 Sep 2007

Publication series

NameProceedings of the European Solid-State Circuits Conference
PublisherIEEE
ISSN (Print)1930-8833

Conference

ConferenceIEEE European Solid State Circuits Conference (ESSCIRC)
CountryGermany
CityMunich
Period01/09/200701/09/2007

Bibliographical note

ISSN: 1930-8833

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  • Cite this

    McCanny, J., Sezer, S., & O'Neill, M. (2007). Exploring Technology Related Design-Space Limitations of High Performance Network Processing. In D. SchmittLandsiedel, & T. Noll (Eds.), ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (pp. 222-231). (Proceedings of the European Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers (IEEE).