Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)

Abstract

A novel Networks-on-Chip (NoC) router architecture specified for FPGA based implementation with configurable Virtual-Channel (VC) is presented. Each pipeline stage of the proposed architecture has been optimized so that low packet propagation latency and reduced hardware overhead can be achieved. The proposed architecture enables high performance and cost effective VC NoC based on-chip system interconnects to be deployed on FPGA.
Original languageEnglish
Title of host publication2011 IEEE International SOC Conference (SOCC)
Place of PublicationNew York
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages302-307
Number of pages6
ISBN (Electronic)978-1-4577-1615-7
ISBN (Print)978-1-4577-1616-4
DOIs
Publication statusPublished - 2011
Event24th IEEE International System-on-Chip Conference (SOCC) - Taipei, Taiwan, Province of China
Duration: 26 Sep 201128 Sep 2011

Conference

Conference24th IEEE International System-on-Chip Conference (SOCC)
CountryTaiwan, Province of China
CityTaipei
Period26/09/201128/09/2011

Cite this

Lu, Y., McCanny, J., & Sezer, S. (2011). Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip. In 2011 IEEE International SOC Conference (SOCC) (pp. 302-307). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/SOCC.2011.6085089