Abstract
This chapter first outlines FastFlow design and then shows sample use of the FastFlow programming environment together with performance results achieved on various state-of-the-art multicore architectures. The FastFlow framework has been designed according to four foundational principles: layered design; efficiency in base mechanisms; support for stream parallelism; and a programming model based on design pattern/algorithmic skeleton concepts. The core of the FastFlow framework provides an efficient implementation of single-producer-single-consumer (SPSC) first in-first out (FIFO) queues. The next tier up extends from one-to-one queues to one-to-many, many-to-one, and many-to-many synchronizations and data flows, which are implemented using only SPSC queues and arbiter threads, thus providing lock-free and wait-free arbitrary dataflow graphs. When designing and implementing new parallel applications using FastFlow, programmers instantiate patterns provided by FastFlow to adapt them to the specific needs of the application at hand. The chapter demonstrates how the principal FastFlow patterns may be used in a parallel application.
Original language | English |
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Title of host publication | Programming Multicore and Many-Core Computing Systems |
Publisher | Wiley-Blackwell |
Pages | 261-280 |
Number of pages | 20 |
ISBN (Electronic) | 9781119332015 |
ISBN (Print) | 9780470936900 |
DOIs | |
Publication status | Published - 27 Jan 2017 |
Keywords
- FastFlow framework
- Lock-free arbitrary dataflow graph
- Multicore architectures
- Stream parallel computations
- Stream parallelism
- Wait-free arbitrary dataflow graph
ASJC Scopus subject areas
- General Computer Science