FAULT-TOLERANT ALGORITHM FOR HIGH-AVAILABILITY AND WAFER SCALE SYSTEMS.

Richard A. Evans, John V. McCanny, John McCanny

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper, the authors have presented one approach to configuring a Wafer-Scale Integration Chip. The approach described is called the 'WINNER', in which bus channels and an external controller for configuring the working processors are not required. In addition, the technique is applicable to high availability systems constructed using conventional methods. The technique can also be extended to arrays of arbitrary size and with any degree of fault tolerance simply by using an appropriate number of cells.
Original languageEnglish
JournalIEE Colloquium (Digest)
Issue number1986 /23
Publication statusPublished - 01 Jan 1986

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

Fingerprint Dive into the research topics of 'FAULT-TOLERANT ALGORITHM FOR HIGH-AVAILABILITY AND WAFER SCALE SYSTEMS.'. Together they form a unique fingerprint.

Cite this