FPGA soft-core processors, compiler and hardware optimizations validated using HOG

Colm Kelly*, Fahad Manzoor Siddiqui, Burak Bardak, Yun Wu, Roger Woods, Karren Rafferty

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor-IPPro was developed and a Histogram of Orientated Gradients (HOG) algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328 fps which represents a 146% speed improvement over the original realization and a tenfold reduction in energy.

Original languageEnglish
Title of host publicationApplied Reconfigurable Computing - 12th International Symposium, ARC 2016, Proceedings
PublisherSpringer-Verlag
Pages78-90
Number of pages13
Volume9625
ISBN (Print)9783319304809
DOIs
Publication statusPublished - 13 Mar 2016
Externally publishedYes
Event12th International Symposium on Applied Reconfigurable Computing, ARC 2016 - Mangaratiba, Brazil
Duration: 22 Mar 201624 Mar 2016

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume9625
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference12th International Symposium on Applied Reconfigurable Computing, ARC 2016
CountryBrazil
CityMangaratiba
Period22/03/201624/03/2016

Keywords

  • FPGA
  • HOG
  • Image processing
  • Memory

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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