There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor - IPPro was developed and a Histogram of Orientated Gradients (HOG) algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328 fps which represents a 146% speed improvement over the original realization and a tenfold reduction in energy.
|Publication status||Published - 24 Mar 2016|
|Event||12th International Symposium on Applied Reconfigurable Computing (ARC) - University of São Paulo, Rio de Janeiro, Brazil|
Duration: 22 Mar 2016 → 24 Mar 2016
|Conference||12th International Symposium on Applied Reconfigurable Computing (ARC)|
|City||Rio de Janeiro|
|Period||22/03/2016 → 24/03/2016|
ASJC Scopus subject areas
- Computer Science(all)
- Signal Processing
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Siddiqui, F. M., 11 Sep 2018
Supervisor: Woods, R. (Supervisor)
Student thesis: Doctoral Thesis › Doctor of PhilosophyFile