FPGA Soft-core Processors, Compiler and Hardware Optimizations validated using HOG

Colm Kelly, Fahad Manzoor Siddiqui, Burak Bardak, Yun Wu, Roger Woods, Karen Rafferty

Research output: Contribution to conferencePaperpeer-review

Abstract

There is demand for an easily programmable, high performance image processing platform based on FPGAs. In previous work, a novel, high performance processor - IPPro was developed and a Histogram of Orientated Gradients (HOG) algorithm study undertaken on a Xilinx Zynq platform. Here, we identify and explore a number of mapping strategies to improve processing efficiency for soft-cores and a number of options for creation of a division coprocessor. This is demonstrated for the revised high definition HOG implementation on a Zynq platform, resulting in a performance of 328 fps which represents a 146% speed improvement over the original realization and a tenfold reduction in energy.
Original languageEnglish
DOIs
Publication statusPublished - 24 Mar 2016
Event12th International Symposium on Applied Reconfigurable Computing (ARC) - University of São Paulo, Rio de Janeiro, Brazil
Duration: 22 Mar 201624 Mar 2016

Conference

Conference12th International Symposium on Applied Reconfigurable Computing (ARC)
CountryBrazil
CityRio de Janeiro
Period22/03/201624/03/2016

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