From bit level systolic arrays to HDTV processor chips

J.V. McCanny; R.F. Woods; J.G. McWhirter

doi:10.1109/ASAP.2006.35

From bit level systolic arrays to HDTV processor chips

J.V. McCanny, R.F. Woods, J.G. McWhirter

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on systolic array architectures. The paper outlines how this has led to the development of highly complex designs for high definition TV and highlights work both on advanced signal processing architectures and tool flows for advanced systems. © 2006 IEEE.

Original language	English
Title of host publication	Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Pages	159-162
Number of pages	4
DOIs	https://doi.org/10.1109/ASAP.2006.35
Publication status	Published - 01 Jan 2006
Event	17th IEEE International Conference on Application-Specific Systems, Architectures and Processors - Steamboat Springs, Co, United States Duration: 01 Sept 2006 → 01 Sept 2006

Conference

Conference	17th IEEE International Conference on Application-Specific Systems, Architectures and Processors
Country/Territory	United States
City	Steamboat Springs, Co
Period	01/09/2006 → 01/09/2006

ASJC Scopus subject areas

General Computer Science

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10.1109/ASAP.2006.35

Cite this

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title = "From bit level systolic arrays to HDTV processor chips",

abstract = "The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on systolic array architectures. The paper outlines how this has led to the development of highly complex designs for high definition TV and highlights work both on advanced signal processing architectures and tool flows for advanced systems. {\textcopyright} 2006 IEEE.",

author = "J.V. McCanny and R.F. Woods and J.G. McWhirter",

year = "2006",

month = jan,

day = "1",

doi = "10.1109/ASAP.2006.35",

language = "English",

pages = "159--162",

booktitle = "Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors",

note = "17th IEEE International Conference on Application-Specific Systems, Architectures and Processors ; Conference date: 01-09-2006 Through 01-09-2006",

}

McCanny, JV , Woods, RF & McWhirter, JG 2006, From bit level systolic arrays to HDTV processor chips. in Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. pp. 159-162, 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Steamboat Springs, Co, United States, 01/09/2006. https://doi.org/10.1109/ASAP.2006.35

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AU - Woods, R.F.

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N2 - The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on systolic array architectures. The paper outlines how this has led to the development of highly complex designs for high definition TV and highlights work both on advanced signal processing architectures and tool flows for advanced systems. © 2006 IEEE.

AB - The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on systolic array architectures. The paper outlines how this has led to the development of highly complex designs for high definition TV and highlights work both on advanced signal processing architectures and tool flows for advanced systems. © 2006 IEEE.

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M3 - Conference contribution

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BT - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

T2 - 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors

Y2 - 1 September 2006 through 1 September 2006

ER -

From bit level systolic arrays to HDTV processor chips

Abstract

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