Fully hardware based WFQ architecture for high-speed QoS packet scheduling

Sakir Sezer; Kieran McLaughlin; Dwayne Burns; Ciaran Toal; Colm McKillen

doi:10.1016/j.vlsi.2011.01.001

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

Sakir Sezer, Kieran McLaughlin, Dwayne Burns, Ciaran Toal, Colm McKillen

Research output: Contribution to journal › Article › peer-review

11 Citations (Scopus)

36 Downloads (Pure)

Abstract

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

Original language	English
Pages (from-to)	99-109
Number of pages	11
Journal	Integration, the VLSI Journal
Volume	45
Issue number	1
DOIs	https://doi.org/10.1016/j.vlsi.2011.01.001
Publication status	Published - Jan 2012

ASJC Scopus subject areas

Hardware and Architecture
Software
Electrical and Electronic Engineering

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10.1016/j.vlsi.2011.01.001

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R1118ECI: Centre for Secure Information Technologies (CSIT)
McCanny, J. V., Cowan, C., Crookes, D., Fusco, V., Linton, D., Liu, W., Miller, P., O'Neill, M., Scanlon, W. & Sezer, S.
01/08/2009 → 30/06/2014
Project: Research

Cite this

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title = "Fully hardware based WFQ architecture for high-speed QoS packet scheduling",

abstract = "A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.",

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AB - A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

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Fully hardware based WFQ architecture for high-speed QoS packet scheduling

Abstract

ASJC Scopus subject areas

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