Generic low-latency NoC router architecture for FPGA computing systems

Research output: Chapter in Book/Report/Conference proceedingChapter

30 Citations (Scopus)

Abstract

A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology. A key feature is that it achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay - a significant enhancement over existing FPGA designs - whilst being very competitive in terms of performance and hardware complexity. It can also be configured in various network topologies including 1-D, 2-D, and 3-D. Detailed design-space exploration has been carried for a range of scaling parameters, with the results of various design trade-offs being presented and discussed. By taking advantage of abundant buildin reconfigurable logic and routing resources, we have been able to create a new scalable on-chip FPGA based router that exhibits high dimensionality and connectivity. The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing systems.
Original languageEnglish
Title of host publicationProceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages82-89
Number of pages8
ISBN (Print)978-1-4577-1484-9
DOIs
Publication statusPublished - 2011
EventIEEE International Conference on Field Programmable Logic and Applications (FPL) - Crete, Greece
Duration: 01 Sept 201101 Sept 2011

Conference

ConferenceIEEE International Conference on Field Programmable Logic and Applications (FPL)
Country/TerritoryGreece
CityCrete
Period01/09/201101/09/2011

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