Abstract
A scheduling method for implementing a generic linear QR array processor architecture is presented. This improves on previous work. It also considerably simplifies the derivation of schedules for a folded linear system, where detailed account has to be taken of processor cell latency. The architecture and scheduling derived provide the basis of a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition.
Original language | English |
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Pages (from-to) | 1097-1100 |
Number of pages | 4 |
Journal | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |
Volume | 2 |
Publication status | Published - 01 Jan 2001 |
Bibliographical note
Copyright 2013 Elsevier B.V., All rights reserved.ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering
- Acoustics and Ultrasonics