Generic scheduling methods for a linear QR array SoC processor

Z. Liu; G. LightBody; R. Walke; Y. Hu; J. McCanny

Generic scheduling methods for a linear QR array SoC processor

Z. Liu
, G. LightBody
, R. Walke
, Y. Hu
, J. McCanny

Research output: Contribution to journal › Article › peer-review

Abstract

A scheduling method for implementing a generic linear QR array processor architecture is presented. This improves on previous work. It also considerably simplifies the derivation of schedules for a folded linear system, where detailed account has to be taken of processor cell latency. The architecture and scheduling derived provide the basis of a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition.

Original language	English
Pages (from-to)	1097-1100
Number of pages	4
Journal	ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Volume	2
Publication status	Published - 01 Jan 2001

Bibliographical note

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering
Acoustics and Ultrasonics

Cite this

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title = "Generic scheduling methods for a linear QR array SoC processor",

abstract = "A scheduling method for implementing a generic linear QR array processor architecture is presented. This improves on previous work. It also considerably simplifies the derivation of schedules for a folded linear system, where detailed account has to be taken of processor cell latency. The architecture and scheduling derived provide the basis of a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition.",

author = "Z. Liu and G. LightBody and R. Walke and Y. Hu and J. McCanny",

year = "2001",

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AU - LightBody, G.

AU - Walke, R.

AU - Hu, Y.

AU - McCanny, J.

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N2 - A scheduling method for implementing a generic linear QR array processor architecture is presented. This improves on previous work. It also considerably simplifies the derivation of schedules for a folded linear system, where detailed account has to be taken of processor cell latency. The architecture and scheduling derived provide the basis of a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition.

AB - A scheduling method for implementing a generic linear QR array processor architecture is presented. This improves on previous work. It also considerably simplifies the derivation of schedules for a folded linear system, where detailed account has to be taken of processor cell latency. The architecture and scheduling derived provide the basis of a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition.

UR - https://www.scopus.com/pages/publications/0034848756

M3 - Article

AN - SCOPUS:0034848756

SN - 1520-6149

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JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

JF - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

ER -

Generic scheduling methods for a linear QR array SoC processor

Abstract

Bibliographical note

ASJC Scopus subject areas

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