Generic SoC QR Array Processor for Adaptive Beamforming

Zhao Hui Liu, John McCanny, G. Lightbody, R. Walke

Research output: Contribution to journalArticlepeer-review

18 Citations (Scopus)


A generic architecture for implementing a QR array processor in silicon is presented. This improves on previous research by considerably simplifying the derivation of timing schedules for a QR system implemented as a folded linear array, where account has to be taken of processor cell latency and timing at the detailed circuit level. The architecture and scheduling derived have been used to create a generator for the rapid design of System-on-a-Chip (SoC) cores for QR decomposition. This is demonstrated through the design of a single-chip architecture for implementing an adaptive beamformer for radar applications. Published as IEEE Trans Circuits and Systems Part II, Analog and Digital Signal Processing, April 2003 NOT Express Briefs. Parts 1 and II of Journal reorganised since then into Regular Papers and Express briefs
Original languageEnglish
Pages (from-to)169-175
Number of pages7
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume50, no 4
Issue number4
Publication statusPublished - Mar 2003

ASJC Scopus subject areas

  • Signal Processing
  • Electrical and Electronic Engineering

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